The physical layout of a very-large scale integration (“VLSI”) design has to adhere to certain design rules. Typically, a Design Rule Checking (DRC) tool is utilized to ensure that a given layout conforms to the set of design rules. The design rules, provided by the manufacturer and specific to a process node, are necessary to ensure the devices are manufacturable and can be produced at an appropriate yield.
If the layout does not adhere to one or more of these rules then the tool has to inform the designer about design rule violations and the designer has to fix each of the design rule violations before the design is considered clean. Design rules are complex in low geometric nodes and different sets of new methodologies are adding to the complexity.
Double patterning technology or DPT is a process which has been adopted for the lower geometric nodes to avoid the resultant geometric distortion due to lithographic issues. At these lower geometric nodes, for example 20 nm technology and below, it is not economically feasible to manufacture integrated circuits (ICs) with the conventional lithographic technology due to the optical resolution limit. When utilizing DPT, alternate masks are used for the printing of images instead of the single mask used in conventional lithographic method. However, although DPT allows the printing of the image at 20 nm or below technology, but it brings associated rules and complexity. One of the complex issues is an “odd loop”, where it is difficult to assign an appropriate mask to print the appropriate image. Accordingly, the detection and visualization of the odd loops in a comprehensive way is a challenge.
Accordingly, what is needed is a method and system for detecting and visualizing odd loops in a DPT process. The method and system should be simple to implement, cost effective and adaptable to existing environments. The present invention addresses such a need.